Device with differential field isolation thicknesses and related methods

ABSTRACT

A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region ( 322 ) that is thinner than a non-nitrided field oxide region ( 324 ). The bird&#39;s beak ( 326 ) of the nitrided field oxide ( 322 ) encroaches less into the active cell region than the bird&#39;s beak ( 328 ) of the thicker non-nitrided field oxide ( 324 ). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the fabrication of integratedcircuit (“IC”) devices, and more particularly to non-uniform localoxidation to achieve differential field oxide thicknesses.

[0002] Local oxidation of silicon (“LOCOS”) is one type of method usedto laterally isolate one device on an integrated circuit substrate fromanother device on the integrated circuit substrate. In a conventionalLOCOS process, a layer of patterned silicon nitride is used as a mask ina thermal oxidation process. Even a thin layer of silicon nitride willprevent significant oxidation from occurring beneath it. The patternedsilicon nitride layer allows field oxide to grow in the “window” regionswhile inhibiting oxide growth in the regions covered by silicon nitride.Unfortunately, oxide growth may occur underneath the edge regions of thesilicon nitride layer to form what is commonly known as a “bird's beak”.

[0003] While silicon nitride is effective in preventing oxygen fromdiffusing through it to the underlying silicon substrate, and hencepreventing the formation of an oxide layer, oxygen can still diffusealong the interface between the silicon nitride and the substrate. Insome instances, a layer of pad oxide underlies the silicon nitride toreduce stress-related defects in the IC, and this pad layer can also actas a conduit for oxygen. In either instance, a bird's beak may formunderneath the silicon nitride layer.

[0004] A desirable characteristic of the LOCOS process is that, afterthe field oxide is formed, the patterned silicon nitride layer can bestripped from the substrate to form what will become active cellsbetween the regions of field oxide. These active cells are self-alignedto the field oxide, thus making efficient use of the valuable substratearea. Unfortunately, a bird's beak intrudes into the active cell region,reducing the area available for active device fabrication. As devicegeometries continue to shrink, the relative portion of the active cellarea consumed by a bird's beak increases, decreasing the ultimate devicedensity of the IC.

[0005] Multi-voltage ICs have an additional problem relating to theformation of bird's beaks. Many devices, such as dynamic random-accessmemories (“DRAMs”) and flash electronically erasable, programmableread-only memories (“flash EEPROMs”) use more than one voltage duringoperation. A low voltage may be used for one type of operation, such asa read/write or sense operation, while a higher voltage is used for aword-line boost operation or a floating-gate program/erase operation.ICs with integrated functions, such as memory and data processingfunctions, may also operate a more than one voltage. It is generallydesirable to minimize the cell size, also known as the design rule, todecrease the IC size and hence cost for a given circuit. However, theability of field oxide to isolate a voltage is generally related to thethickness of the field oxide. Unfortunately, the size of a bird's beakis generally related to the thickness of the field oxide that is grown.Therefore, field oxide that is thick enough to withstand the highervoltage results in an undesirably large bird's beak intruding into theactive cell area of the lower voltage devices. Conversely, a field oxideoptimized for the design rule of low-voltage cells might not reliablyisolate high-voltage cells.

[0006] Therefore a multi-voltage IC with field oxidation that reliablyisolates high voltages while allowing tighter design rules forlow-voltage cells is desirable.

SUMMARY OF THE INVENTION

[0007] The present invention provides devices with differential filedoxide thicknesses and methods for making such devices. In oneembodiment, a layer of silicon oxide is formed on a surface of a siliconsubstrate. A silicon nitride layer is formed over the layer of siliconoxide, and the silicon nitride layer is patterned to expose selectedregions of the layer of silicon oxide. Selected regions of the exposedsilicon oxide are covered with a mask, and the remaining exposed regionsof the silicon oxide layer are nitridized by implanting nitrogen intothe silicon oxide layer and/or silicon substrate. The mask is strippedand field oxide is grown in the exposed regions of the silicon oxidelayer. During the field oxide growth process, the nitridized regionsform silicon oxy-nitride, which inhibits oxide growth compared to thenon-nitrided regions. After the field oxidation process, the field oxideis thicker in the non-nitrided regions than in the nitrided regions. Ina particular embodiment, the non-nitrided field oxide regions are usedto isolate an active cell containing a high-voltage memory device of aflash EEPROM memory cell from an active cell containing a low-voltageselect transistor, and to isolate high-voltage active cells from eachother and from low-voltage cells. The nitrided field oxide is used toisolate active cells containing low-voltage devices from each other. Thehigh voltage is between about 8-9 V, and the low voltage is betweenabout 3-5 V. In another embodiment, the exposed regions of the siliconoxide layer are nitrided by applying a substance that acts as a nitrogensource, such as dilute aqueous ammonia, to the exposed regions.

[0008] In another embodiment, the silicon nitride layer is patterned toexpose a first set of regions of the silicon oxide layer. The first setof regions are nitrided by thermally treating the layer of silicon oxidein a nitrogen rich environment, such as an environment includingammonia. The silicon nitride layer is then patterned again to expose asecond set of regions of the silicon oxide layer. Field oxide is grownin both the nitrided and non-nitrided exposed regions of the siliconoxide layer, the field oxide being thinner in the former than in thelatter. In another embodiment, there is no layer of silicon oxide in thewindows of the silicon nitride layer and the surface of the siliconsubstrate is nitrided.

[0009] These and other embodiments of the present invention, as well assome of its advantages and features are described in more detail inconjunction with the text below and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIGS. 1A-1C are simplified cross sections of portions of an ICillustrating the effect of bird's beak encroachment;

[0011]FIG. 2 is a simplified cross section of a portion of an IC withdifferential field oxide thicknesses according to one embodiment of thepresent invention;

[0012] FIGS. 3A-3D are simplified cross sections of a portion of an ICas it is processed to produce a differential field oxide thicknessaccording to another embodiment of the present invention;

[0013] FIGS. 4A-4D are simplified cross sections of a portion of an ICas it is processed to produce a differential field oxide thicknessaccording to another embodiment of the present invention;

[0014] FIGS. 5A-5D are simplified cross sections of a portion of an ICas it is processed to produce a differential field oxide thicknessaccording to another embodiment of the present invention;

[0015]FIG. 6 is a simplified circuit diagram of portion of a flashmemory device adaptable for use with the present invention;

[0016]FIG. 7 is a simplified top view of a portion of a flash memorydevice according to one aspect of the present invention;

[0017]FIG. 8 is a simplified cross section of a flash memory deviceaccording to one aspect of the present invention; and

[0018]FIG. 9 is a simplified cross section of another flash memorydevice according to one aspect of the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

[0019] The present invention provides a technique, including methods anddevices, for manufacturing an integrated circuit device. In an exemplaryembodiment, the present invention provides a technique for isolatingactive cells, or devices, in a multi-voltage integrated circuit, such asa flash memory device.

[0020] Many ICs, such as flash memories and DRAMs, utilize more than oneoperating voltage. The lower voltage is usually in the range of betweenabout 3-5 V, but could be higher or lower depending on the type and/orsize of the basic logic, switching, select, and other devicesincorporated in the IC. The lower voltage is often called V_(DS),V_(CC), or the like. A higher voltage is also used for certainoperations, such as opening or pumping word lines (e.g. V_(PP) in aDRAM) or programming or erasing flash memory cells (e.g. in a flashmemory). The higher voltage may be supplied from an external source, ormay be generated internally, that is, generated on the IC chip from thelower voltage. A charge-transfer pump circuit, for example, may be usedto generate the higher voltage on the IC chip from the lower voltage.The higher voltage may range from a few volts higher than the lowervoltage to more than twice as high as the lower voltage. In a flashmemory device, for example, the program/erase voltage may be betweenabout 8-9 volts.

[0021] To incorporate such high voltages in an IC, the field oxidethickness has to be sufficiently thick to avoid field turn-on. In aLOCOS or modified LOCOS process, fabricating a thicker field oxidecreates a thicker and larger bird's beak region. The larger bird's beakregion intrudes further into the active cell area, limiting the cellarea available for device fabrication, or more likely, requiring alarger cell area to accommodate the larger bird's beak region.

[0022] FIGS. 1A-1C are simplified cross sections of portion of an IC 100where an active cell is isolated from adjacent cells by field oxide. InFIG. 1A, an active cell region for low-voltage devices 102 and an activecell region for high-voltage devices 104 are separated by field oxide106. The active cells are shown as being different sized solely forpurposes of illustration. The field oxide is an appropriate thicknessfor isolating low voltage cells. This produces a minimal bird's beak 108and maximizes the active cell area.

[0023] In FIG. 1B, the field oxide 110 has been grown to a thicknesssuitable for isolating high-voltage devices. The bird's beak 112 extendsfurther into the active cell region, reducing the area cell areaavailable for device fabrication. FIG. 1C is an extension of FIG. 1Bwhere the bird's beaks 114, 116 have grown together, thus consuming theentire active cell area.

[0024]FIG. 2 is a simplified cross section of a portion of an IC device100 according to one aspect of the present invention. Field oxide of afirst thickness 202 has been grown concurrently with nitrided fieldoxide of a second thickness 204. The first thickness is greater than thesecond thickness, providing suitable isolation for high voltages, whileresulting in less active cell area lost to bird's beak formation in thelow-voltage cells.

[0025] FIGS. 3A-3D are simplified cross sections of a portion of an ICdevice 300 as the device is processed to result in differentialthicknesses of field oxide. FIG. 3A shows the portion of the IC with apad layer of silicon oxide 302 overlying a silicon substrate or siliconfilm 304. The pad layer is optional, and may be stripped from thewindows 306 in the silicon nitride layer 308, or omitted entirely. Alayer of silicon nitride 308 has been deposited over the pad layer andpatterned by any of several known methods to define field oxide regions310, 312 and what will become self-aligned low-voltage active cells 314and high-voltage active cells 316.

[0026]FIG. 3B shows the portion of the IC device 300 after a layer ofphotoresist 320 has been formed and patterned over the patterned siliconnitride layer 308. The term “photoresist” is used in a generic sense,and is meant to incorporate e-beam resists and similar materials thatare used for masking selected areas of a substrate. The patternedphotoresist acts as a mask to cover some of the field oxide regions 312,while leaving other field oxide regions 310 exposed. The exposed fieldoxide regions 310 are nitridized by implanting nitrogen 318 using an ionimplantation process. In this instance, N₂ was used as precursor in aconventional ion beam implantation process. Other precursors may beused, such as ammonia, or a nitrate or nitrite source, and otherimplantation processes may by used, such as plasma source ionimplantation. The nitrogen may be implanted into the pad layer 302 ofsilicon oxide or the silicon 304, or both, depending on the implantationenergy and temperature of the substrate.

[0027]FIG. 3C shows the portion of the IC device 300 after the photoresist has been stripped. The exposed field oxide region 310 has beennitridized, illustrated by a stippled area 322, by the nitrogen implant.The non-exposed field oxide regions 312 have not been nitridized. FIG.3D shows the portion of the IC device after a single field oxidationstep and silicon nitride strip. Thin field oxide has grown in thenitridized areas 322, and thicker field oxide has grown in thenon-nitridized areas 324. The thinner field oxide has less of a bird'sbeak 326 than the bird's beak 328 of the thicker field oxide, resultingin more efficient use of the active cell area.

[0028] The thicker field oxide 324 is between about 3,000-8,000 Å thickand the thinner field oxide 322 is between about 1,000-3,000 Å thick.These field oxides form isolation regions of different thicknesses. Theisolation regions are used to separate, for example, a high voltageregion from a low voltage region. The high voltage region is for avoltage which exceeds, for example, a switching voltage for the lowvoltage (memory) region. The ratio between this high voltage and theswitching voltage ranges from greater than about 1.5, or greater thanabout 2, or greater than about 3, or greater than about 4.5, or greaterthan about 6, in embodiments of the present invention, but is notlimited to these values. A ratio of the thickness of the thicker fieldoxide to the thickness of the thinner field oxide ranges from valuesgreater than about 1.5, or greater than about 2, or greater than about3, or greater than about 4.5, or greater than about 6, in specificembodiments of the invention, but is not limited to these values.

[0029] FIGS. 4A-4D are simplified cross sections of a portion of an ICdevice 400 as the device is processed to result in differentialthicknesses of field oxide according to another embodiment of thepresent invention. FIG. 4A shows the portion of the IC device 400 afterthe silicon nitride oxidation mask layer 408 has been patterned on asilicon film or substrate 404 and a layer of resist 420 has been appliedand patterned over the mask layer 408 to cover some of the field oxideareas 412, while leaving the remaining field oxide areas 410 exposed.The photoresist may be the same as, or different than, the photoresistused in the ion-implantation process discussed in conjunction with FIGS.3A-3D.

[0030]FIG. 4B is a simplified cross section of the portion of the ICdevice 400 after a nitridizing material has been applied to the exposedportions of the field oxide areas 410. The nitridizing material may beaqueous ammonia or a solution of ammonium nitrate and water, forexample. The nitridizing material may be applied by a variety ofmethods, including spraying, dipping, or spinning. For illustrationpurposes, a layer of nitridizing material 422 is shown overlying theexposed field oxide areas, but it is understood that the nitridizingmaterial may be bound, absorbed, or otherwise incorporated into theunderlying material, which is in this case silicon oxide of the optionalpad layer 402, and may be otherwise affixed to the silicon nitride maskand photoresist layers. Although the nitridizing layer 422 is shown as acohesive layer, it is actually more of a porous residue.

[0031]FIG. 4C is simplified cross section of the device after thephotoresist has been stripped, exposing the non-nitridized field oxideregion 412. An organic solvent was used to strip the photoresist,leaving the nitridizing material 422 in the nitridized field oxideregion 410. The organic solvent easily permeates the ionic nitridizingmaterial to dissolve the photoresist and lift off the overlyingnitridizing material. FIG. 4D is a simplified cross section of theportion of the IC device 400 after a single field oxide growth step. Thefield oxide in the nitridized regions 423 is thinner than the fieldoxide in the non-nitridized regions 424.

[0032] Alternatively, a nitridizing material may be deposited asdescribed above or with another process, such as a chemical vapordeposition process. A photolithgraphic process and etch or wash is thenused to selectively remove the nitridizing material, leaving it in thewindows in the oxidation mask where thin field oxide is desired.

[0033] FIGS. 5A-5D are simplified cross sections of a portion of an ICdevice 500 as the device is processed to result in differentialthicknesses of field oxide according to another embodiment of thepresent invention. FIG. 5A shows a silicon substrate or film 504 with anoxidation mask layer 508, such as silicon nitride layer. As discussedabove in conjunction with FIGS. 3A-3D, a pad layer of silicon oxide (notshown in this embodiment) may lie between the oxidation mask layer andthe silicon substrate. The oxidation mask layer is patterned using knowntechniques to form a first pattern, represented by exposed areas ofsilicon 510.

[0034]FIG. 5B shows the exposed areas being nitridized with an ion beam514 formed from N₂. Of course, other methods for nitridizing may beemployed, as discussed above. If, for example, a nitridizing material isapplied, the material may be driven into the silicon by a thermaltreatment, as the oxidizing mask can typically withstand highertemperatures, or a thermal treatment may be performed in a nitridizingatmosphere, such as by heating the substrate in an ammonia-containingatmosphere, with or without oxygen or water vapor (steam).

[0035]FIG. 5C shows the portion of the IC after a nitridizing region 522has been formed and after a second set of field oxide regions 512 hasbeen exposed by a second patterning process of the oxidation mask layer508. As discussed above, the nitridizing may be incorporated within thesubstrate material, or may be a region of material lying on thesubstrate. It is shown as being within the substrate solely forconvenience of illustration. FIG. 5D shows the portion of the IC after asingle field oxidation process. The field oxide in the nitrided areas523 is thinner than the field oxide in the non-nitrided areas 524.

[0036]FIG. 6 is a schematic circuit diagram of a memory cell accordingto an embodiment of the present invention. With reference to FIG. 6, amemory cell of the present invention includes a memory device 611 and afield effect transistor 613 which allows selection of memory device 611from among other memory cells. A drain 615 of selection transistor 613is connected via a metal contact 631 to a read line 629. Selectiontransistor 613 and memory device 611 are connected together in series ata node 617 which serves as both a source for selection transistor 613and a drain for memory device 611. A source 619 of memory device 611connects to a common source line which in turn is coupled to ground. Thegate 621 of selection transistor 613 is electrically connected to a wordselect line. The control gate 623 of memory device 611 is connected to asense enable and program line. The circuit of FIG. 6 also includes inthe memory device 611 a floating gate 626 separated from the substrateby a gate oxide layer, which is typically very thin, between about50-300 Å and represented in FIG. 6 by a dashed line 626. A program anderase implant 627 is provided in memory device 627 proximate to thedevice 617. The gate oxide layer together with the program and eraseimplant 627 permit rapid erasure of the memory device 611 electricallyin a few milliseconds, instead of the usual twenty minutes or so with UVlight with prior memory devices. The implant 627 also enables moreefficient reprogramming to occur. As will be seen below, the memory celllayout and fabrication process of the present invention provides for asmaller size memory cell and associated isolation region.

[0037]FIG. 7 is a top plan view of the memory cell of FIG. 6. FIG. 8 isa side sectional view taken along the line 603-603 in FIG. 7. Withreference to FIGS. 7 and 8, a semiconductor chip having an array ofmemory cells comprises a semiconductor substrate 633 with active memoryareas 635 therein. A field isolation oxide layer 637 is present over allnonactive areas outside of memory areas 635. Three spaced-apart implants615, 617 and 619 are located in memory area 635 with channel areas 639and 641 defined therebetween. Implant 615 forms a drain for theselection transistor 613 in the circuit of FIG. 6. Implant 617 forms anode functioning as both a source for selection transistor 613 and adrain for memory device 611 in FIG. 6. Implant 619 forms a source formemory device 611. While substrate 633 is typically P-type and implants615, 617 and 619 are N-type.

[0038] A program and erase implant 627 is also present in the activememory area 635 of substrate 633. Implant 627 overlaps part of nodeimplant 617, extending into channel 641 between implants 617 and 619 ofthe memory device 611. Implant 627 is N-type in this instance, and maybe formed by either phosphorus or arsenic ion implantation followed bydiffusion, as explained below. A thin oxide layer 625 is disposed overchannel 641 between implants 617 and 619, including over the portion ofprogram and erase implant 627 which extends into channel 641, in activearea 635. Typically, thin oxide layer 625 is between 70 Angstroms and150 Angstroms thick. The remainder of active area 635 between fieldoxide layer 637 has an oxide layer 622 over it. Oxide layer 622 isthicker than thin oxide layer 625, typically about 300-500 Angstromsthick.

[0039] A polysilicon floating gate 626 is disposed on thin oxide layer625 and extends over that portion of program and erase implant 627 thatis beneath thin oxide layer 625. An interpoly oxide layer 624 isdisposed on floating gate 626 and a polysilicon sense gate 623 issituated above interpoly oxide layer 624. A polysilicon select gate 621is disposed above channel 637 between implants 615 and 617. The entirewafer is covered with an insulating glass layer 639 with vias forcontacts 631 therein. A layer of conductive lines 629 is disposed on topof glass layer 640.

[0040] In addition to the field isolation layer 637, there is anotherfield isolation layer 837 that is thicker than the layer 637. Theisolation layer 837, isolates a high voltage active region 803. Theisolation layer 837 is made, along with at least nearby portions of theisolation layer 637 according to the single oxidation process describedabove with respect to earlier figures.

[0041] In a specific embodiment, the present invention also can beapplied to an improved flash memory cell 900, such as the one shown inthe simplified diagram of the FIG. 9, for example. This diagram ismerely an illustration and should not limit the scope of the claims. Oneof ordinary skill in the art would recognize other variations,alternatives, and modifications. Memory cell 1000 is defined insubstrate 1001, which includes an upper surface 1003 that issubstantially planar in geometry. A well region 1005 is defined in thesubstrate. The well region 1005 has a drain region 1007 and a sourceregion 1009. In some embodiments, the drain region is a common drainregion, which is shared by another memory cell. Similarly, the sourceregion can be a common source region, which is shared by another memorycell. Between the source region and the drain region is a channel region1011. The source and drain regions are made using implantationtechniques, but can also be made using plasma immersion ion implantationor the like. A dielectric layer 1013, including a gate dielectric layer1015 and a tunnel dielectric layer 1017, is defined overlying thechannel region 1011. These dielectric layers can be made using asuitable material including silicon dioxide, silicon nitride, siliconoxy-nitride, and others. In the context of this embodiment, the gatedielectric and tunnel dielectric layers are made of high quality silicondioxide. The tunnel dielectric layer is substantially uniform andsubstantially pinhole free. Additionally, the tunnel dielectric layercan withstand numerous programming and erase cycles.

[0042] The memory cell 1000 also includes a novel gate structure 1019.In particular, the gate structure 1019 includes a select gate 1021,which is defined from a first polysilicon layer, e.g., poly-1. Theselect gate is made from a polysilicon layer that is doped using N-typeimpurities. In some embodiments, the impurities are diffused using aPOCl₃ compound or the like. Alternatively, the gate can be in-situ dopedusing a phosphorous bearing compound or the like. In furtherembodiments, the polysilicon layer can be laid in an amorphous state,which is later crystallized. The amorphous state generally produces asmoother polysilicon layer. The select gate overlies gate oxide andextends to the drain region. A sidewall spacer 1023 and an overlyinginsulating layer 1025 are defined overlying the select gate. Thesidewall spacer and the insulating layer insulate and isolate the selectgate from overlying circuit elements, e.g, control gate, floating gate.The select gate also has a channel region ranging from about 0.2 micronand less or about 1.0 micron and less, but is not limited to theseranges. Additionally, the select gate has a thickness of about 500Angstroms and less and about 3500 Angstroms and less, but is not limitedto these ranges.

[0043] The gate structure 1019 also includes a split floating gate 1027overlying a portion of the upper surface of the substantially planarsubstrate, and also overlaps a portion of the select gate, which isdefined overlying the planar surface of the substrate. That is, thesplit floating gate is defined overlying insulating layer 1025, whichforms overlying the top surface of the select gate. The split gate alsooverlies an edge(s) including sidewall spacer 1023 of the select gate.

[0044] The split gate 1019 also has an edge 1029 overlying a region onthe top surface of the split gate. Split floating gate 1019 also extendsfrom the select gate to a region overlying tunnel dielectric layer 1017and extends to source region 1009. Accordingly, the split gate has atleast three regions, including a lower horizontal region 1027A overlyingthe planar surface (which includes the tunnel oxide and the source/drainregion), a vertical region 1027B overlying an edge or sidewall spacer ofthe select gate, and an upper horizontal region 1027C overlying the topsurface of the select gate. The lower horizontal region 1027A, thevertical region 1027B, and the upper horizontal region 1027C define thesplit gate structure.

[0045] The split gate 1027 can be made of any suitable material such as,for example, polysilicon, e.g., poly-2. In most embodiments, the splitgate is made from a polysilicon layer that is doped using N-typeimpurities. In some embodiments, the impurities are diffused using aPOCl₃ compound or the like. Alternatively, the floating gate can bein-situ doped using a phosphorous bearing compound or the like. Infurther embodiments, the polysilicon layer can be laid in an amorphousstate, which is later crystallized, rather than the polycrystallinestate. The amorphous state generally produces a smoother polysiliconlayer.

[0046] A dielectric layer(s) 1031 is defined overlying the floatinggate. The dielectric layer forms along edges of the floating gate, whichare over the select gate. Additionally, the dielectric layer overliesthe top surface of the upper horizontal region, overlies an outersurface of the vertical region, and extends over the lower horizontalregion of the floating gate structure. Of course, the type of dielectriclayer used depends highly upon the size and shape of the floating gateand control gate. The dielectric layer 1031 can be any suitable layer orcombinations of layers such as an oxide-on-nitride-on-oxide, which iscommonly termed “ONO.” The dielectric layer can also be a single nitridelayer or a single oxide layer depending upon the application. Either CVDor thermal techniques can be used to form the dielectric layer orlayers. The dielectric layer insulates and isolates the floating gatefrom a control gate 1033.

[0047] Control gate 1033 forms overlying the dielectric layer 1031,which is sandwiched between the floating gate and the control gate. Thecontrol gate is defined overlying edge 1029 of the floating gate, whichis over a top portion of the select gate. The control gate also formsoverlying the upper horizontal region, the vertical region, and thelower horizontal region of the floating gate. The control gate can bemade of any suitable material such as, for example, polysilicon, e.g.,poly-3. In most embodiments, the control gate is made from a polysiliconlayer that is doped using N-type impurities. In some embodiments, theimpurities are diffused using a POCl₃ compound or the like.Alternatively, the control gate can be in-situ doped using a phosphorousbearing compound or the like. In further embodiments, the polysiliconlayer can be laid in an amorphous state, which is later crystallized,rather than the polycrystalline state. The amorphous state generallyproduces a smoother polysilicon layer.

[0048] A contact 1035 is defined overlying the drain region. Contactsare also defined on the select gate, the control gate, and the sourceregion. These contacts can be made using a variety of techniques. Forexample, the contacts can be made using a combination of metals such asaluminum with a barrier metal such as titanium nitride, titaniumtungsten, and others. Alternatively, the contacts can be made using atungsten layer or copper layer with a barrier metal. Furthermore, thecontacts can be made from “plugs” such as tungsten plugs, polysiliconplugs, aluminum plugs, and the like. The plugs can be used with orwithout a barrier layer, or can also be grown in a selective manner. Ofcourse, the type of contacts used depends highly upon the application.

[0049] An isolation region 637 separates isolates the FLASH cell 1000. Asecond isolation 837, which is thicker than the isolation region 637,isolates a high voltage active region 803. The voltage for the highvoltage active region 803 is higher than the voltage for the cell 1000.The isolation regions 637 and 837 are made according to the processdescribed above with respect to earlier figures. It is understood that ahigh voltage active region may be operated at a lower voltage in someapplications, and that such a cell may still have thicker isolation.That is, the thicker oxide provides greater isolation, but may not benecessary, depending on the cell operation condition.

[0050] In the present embodiment, the gate coupling ratio (“GCR”) isincreased by way of the present novel transistor design. GCR increasesby increasing the area of the floating gate that is capacitively coupledto the control gate relative to the area of the floating gate that iscapacitively coupled to the tunnel oxide overlying the active cellregion. As shown, the control gate couples to the floating gate throughexposed surfaces of edge 1029, upper horizontal region 1027C, andvertical region 1027B. Floating gate couples to the tunnel oxide throughthe lower horizontal region 1027A. Accordingly, control gate couples tothe floating gate through at least two additional surface regions.Ideally, GCR approaches one in embodiments of the present invention.Practically, however, it is quite difficult for GCR to equal one.Accordingly, GCR ranges from values greater than 0.3, or greater than0.5, or greater than 0.6, or greater than 0.8 in the embodiments of thepresent invention, although GCR is not limited to these values. Theexact value of GCR depends upon the particular geometric configurationof the floating gate as well as the design rule of the device. Ofcourse, the final GCR value will depend upon the particular application.

[0051] In a specific embodiment, the present memory cell can beprogramed and erased by placing voltages on selected gate structures. Toprogram the floating gate or add electrons to the floating gate,selected voltages are applied to the gate structures and source/drainregions. Electrons migrate from the source region through the channelregion and inject through the tunnel oxide layer to the floating gate,where electron charge builds up. To erase the floating gate or removeelectrons from the floating gate, selected voltages are applied to thegate structures and the source/drain regions. Electrons migrate from thefloating gate through the tunnel oxide layer to the channel region andout through the drain region.

[0052] While the above is a complete description of specific embodimentsof the present invention, various modifications, variations, andalternatives may be employed. For example, the substrate could be asemiconductor-on-insulator (“SOI”) type of wafer, or a wafer other thana silicon wafer. The present invention may be adapted to other types ofsubstrates or devices with appropriate selection of materials andprocesses, and these and other variations will be apparent to persons ofskill in the art. These equivalents and alternatives are intended to beincluded within the scope of the present invention. Therefore, the scopeof this invention should not be limited to the embodiments described,and should instead be defined by the following claims.

What is claimed is:
 1. A method for producing an intermediatesemi-conductor device structure, the method comprising: (a) patterningan oxidation mask layer disposed on a substrate to create a first windowregion and a second window region, then; (b) forming a layer of resiston the oxidation mask layer, (c) patterning the layer of resist to coverthe second window region and not the first window region, then; (d)nitridizing the first window region, the second window region remainingnon-nitridized, then; (e) stripping the layer of resist from the oxidelayer; (f) oxidizing the substrate to form a nitridized field oxide inthe first window region and a non-nitridized field oxide in the secondwindow region, the nitridized field oxide being thinner than thenon-nitridized field oxide; and (g) stripping the oxidation mask fromthe substrate.
 2. The method of claim 1 wherein the step (d) ofnitridizing is performed by an implantation process.
 3. The method ofclaim 1 wherein the step (d) of nitridizing is performed by applying anitrogen source to at least the first window region.
 4. The method ofclaim 1 where the step (f) of oxidizing the substrate is a single fieldoxidation step.
 5. The method of claim 4 where the step (f) produces anon-nitridized field oxide thickness of between about 3,000-8,000 Å anda nitridized field oxide thickness of between about 1,000-3,000 Å. 6.The method of claim 5 wherein the non-nitridized field oxide thicknessis at least about 1.5 times the nitridized field oxide thickness.
 7. Amethod for producing an intermediate flash memory semiconductor devicestructure, the method comprising: (a) patterning an oxidation mask layerdisposed on a substrate to create a first window region and a secondwindow region, the first window region adjoining a low-voltage activecell and the second window region adjoining a high-voltage active cell,then; (b) forming a layer of resist on the oxidation mask layer, (c)patterning the layer of resist to cover the second window region and notthe first window region, then; (d) implanting nitrogen to nitridize thefirst window region, the second window region remaining non-nitridized,then; (e) stripping the layer of resist from the oxide layer; (f)oxidizing the substrate to form a nitridized field oxide in the firstwindow region and a non-nitridized field oxide in the second windowregion, the nitridized field oxide being at least about 20% thinner thanthe non-nitridized field oxide; and (g) stripping the oxidation maskfrom the substrate.
 8. A method for producing an intermediatesemi-conductor device structure, the method comprising: (a) patterningan oxidation mask layer disposed on a substrate to create a first windowregion, then; (b) nitridizing at least the first window region; (c)patterning the oxidation mask layer to create a second window region,then; (d) oxidizing the substrate to form a nitridized field oxide inthe first window region and a non-nitridized field oxide in the secondwindow region, the non-nitridized field oxide being at least about 1.5times thicker than the nitridized field oxide; and (e) stripping theoxidation mask from the substrate.
 9. The method of claim 8 wherein thestep (b) of nitridizing is performed by an implantation process.
 10. Themethod of claim 8 wherein the step (b) of nitridizing is performed byapplying a nitrogen source to at least the first window region.
 11. Asemiconductor device comprising: a nitrided field oxide region having anitrided field oxide thickness; a non-nitrided field oxide region havinga non-nitrided field oxide thickness, the nitrided field oxide thicknessbeing less than the non-nitrided field oxide thickness.
 12. Thesemiconductor device of claim 11 wherein the nitrided field oxide regionand the non-nitrided field oxide region result from a single fieldoxidation process.
 13. The semiconductor device of claim 12 wherein thenitrided field oxide region has a nitrided oxide thickness of betweenabout 1,000-3,000 Å and the non-nitrided field oxide region has anon-nitrided oxide thickness of between about 3,000-8,000 Å.
 14. Thesemiconductor device of claim 12 wherein the non-nitrided oxidethickness is at least about 1.5 times the nitrided oxide thickness. 15.The semiconductor device of claim 12 wherein the non-nitrided oxidethickness is at least about 2 times the nitrided oxide thickness. 16.The semiconductor device of claim 12 wherein the non-nitrided oxidethickness is at least about 3 times the nitrided oxide thickness. 17.The semiconductor device of claim 12 wherein the non-nitrided oxidethickness is at least about 4.5 times the nitrided oxide thickness. 18.The semiconductor device of claim 12 wherein the non-nitrided oxidethickness is at least about 6 times the nitrided oxide thickness. 19.The semiconductor device of claim 11 wherein the semiconductor device isa multi-voltage semiconductor device designed to operate at a firstvoltage and a second voltage, the second voltage being greater than thefirst voltage.
 20. The semiconductor device of claim 19 wherein thesecond voltage is at least about 1.5 times greater than the firstvoltage.
 21. The semiconductor device of claim 19 wherein the secondvoltage is at least about 2 times greater than the first voltage. 22.The semiconductor device of claim 19 wherein the second voltage is atleast about 3 times greater than the first voltage.
 23. Thesemiconductor device of claim 19 wherein the second voltage is at leastabout 4.5 times greater than the first voltage.
 24. The semiconductordevice of claim 19 wherein the second voltage is at least about 6 timesgreater than the first voltage.
 25. The semiconductor device of claim 19wherein the semiconductor device is a flash memory device.
 26. Thesemiconductor device of claim 19 further comprising a low-voltage celland a high-voltage cell, the nitrided field oxide providing isolation tothe low-voltage cell and the non-nitrided field oxide providingisolation to the high-voltage cell.
 27. The semiconductor device ofclaim 19 wherein the second voltage is at least about twice the firstvoltage.
 28. The semiconductor device of claim 11 wherein thenon-nitrided field oxide thickness is at least about 20% greater thanthe nitrided field oxide thickness.
 29. A flash-memory semiconductordevice comprising: a low-voltage active cell configured to operate at afirst voltage; a high-voltage active cell configured to operate at asecond voltage, the second voltage being at least about twice the firstvoltage; a nitrided field oxide region adjoining the low-voltage activecell, the nitrided field oxide having a nitrided field oxide thickness;a non-nitrided field oxide region adjoining the high-voltage activecell, the non-nitrided field oxide having a non-nitrided field oxidethickness, the non-nitrided field oxide thickness being at least about20% thicker than the nitrided field oxide thickness.